RE: EXTERNAL: Re: [vhdl-200x] Standard Package enhancements

I wrote is1() and is0() functions for my personal library long ago.  They interpret H/L as 1/0, and warn on other meta-values (and return false).

Doesn’t an aggregate’s range default to index_range‘low to … or … downto index_range‘low? Integer’low is pretty ugly for a default. Using comma separated lists of element values in aggregates is very effective in OSVVM, which uses integer_vector extensively.

The only standard types where negative integer index ranges are used are fixed and floating point types where the numerical weight is based on index value (and therefore literal aggregates are highly discouraged for them.)


Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control
Dallas TX



From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Daniel Kho
Sent: Thursday, April 16, 2015 10:38 AM
To: vhdl-200x@eda.org
Subject: EXTERNAL: Re: [vhdl-200x] Standard Package enhancements

Yes, I have something similar to the active_high() and active_low() functions you have as well. Perhaps it's time for us to standardize these?
"Because boolean_vector can't support negative ranges, I had to change this to std_ulogic_vector or unsigned instead."
I meant I had to create my own types instead (e.g. I have a type called t_flag).
std_ulogic_vector's range is also (natural range <>). I'm not sure if it's a good idea to expand all these ranges to (integer range <>)? For std_ulogic_vector, unsigned, and signed?
-Daniel

On 16 April 2015 at 21:01, Martin.J Thompson <Martin.J.Thompson@trw.com<mailto:Martin.J.Thompson@trw.com>> wrote:
I wrote to_stdulogic and to_stdulogicvector functions for these, and can share them if there's a place for me to deposit the source.

[MJT] Feel free to send me a pull request to my random collection of VHDL functions here if you like:
https://github.com/martinjthompson/libv


Cheers,
Martin

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