Re: [vhdl-200x] Standard Package enhancements

From: Daniel Kho
Sent: Apr 16, 2015 7:06 AM
To: "vhdl-200x@eda.org"
Subject: [vhdl-200x] Standard Package enhancements

Hi all,

There are a few enhancements I would like to propose for some of our standard packages. Do let me know what you think.

standard.vhd:
    type BOOLEAN_VECTOR is array (INTEGER range <>) of BOOLEAN;
    type BIT_VECTOR is array (INTEGER range <>) of BIT;
    type INTEGER_VECTOR is array (INTEGER range <>) of INTEGER;
    type REAL_VECTOR is array (INTEGER range <>) of REAL;
    type TIME_VECTOR is array (INTEGER range <>) of TIME;
...snip...

Because boolean_vector can't support negative ranges, I had to change this to std_ulogic_vector or unsigned instead.

Have type conversion functions, or better, make conversions implicit between the following types:

    boolean <-> bit

    boolean <-> std_ulogic

    boolean_vector <-> std_ulogic_vector

    boolean_vector <-> bit_vector

    boolean_vector <-> unsigned
...snip...

...snip...