[vhdl-200x] Relax locally static restrictions?

Hi all,
I'm wondering if there is a reason to only allow locally static expressions
in array aggregates? Why can't we pass generic constants from a higher
level hierarchy to form the expressions for choices in array aggregates?

I find the LRM rather restrictive in how named associations of array
aggregates are only "allowed to have a choice that is not locally static,
or likewise a choice that is a null range, only if the aggregate includes a
single element association and this element association has a single
choice".

Is there some history on why such a restriction is in place?

----------------------------------------------------------------------------------------------------------
Section 9.3.3.3 Array aggregates
Apart from a final element association with the single choice others, the
rest (if any) of the element
associations of an array aggregate shall be either all positional or all
named. A named association of an array
aggregate is allowed to have a choice that is not locally static, or
likewise a choice that is a null range, only
if the aggregate includes a single element association and this element
association has a single choice. An
others choice is locally static if the applicable index constraint is
locally static.
----------------------------------------------------------------------------------------------------------

I find many FPGA designers (myself included) would like to be able to do
the following, i.e. be able to pass a globally static generic into a
discrete range of an array aggregate. However, I believe the LRM only
allows locally static discrete ranges for the choices in array aggregates.
However, we would like to be able to have globally static discrete ranges
as well. Is there something stopping us from doing the following?

entity test is
    generic(width: integer := 10; lanes: integer := 8);
    port(
        in1: in std_ulogic_vector(width*lanes-1 downto 0);
        q: out std_ulogic
    );
end entity test;

architecture rtl of test is
    constant mask: std_ulogic_vector(width*lanes-1 downto 0) :=
(width*lanes-1 downto width => '0', others => '1');
begin
    q <= '1' when (in1 and mask) = mask else '0';
end architecture rtl;

One simulator issued me a warning while another issued me an error. The
warning quotes Section 9.3.3.3 of the LRM, while the error insists that the
discrete range must be locally static. IMO, both are correct as per the
LRM, but why such a restriction in the first place?

Best regards,
Daniel

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