Hi all, One of my peeves with VHDL as it stands is that report statement include "the name of the design unit containing the port statement". In many cases, the design unit is a package containing a multi-purpose procedure, such as numeric_std. One of the times this causes me much annoyance is when I get warnings of metavalues from numeric_std, the report statement gives me no clue as to which part of my design is "defective". I care not where the report statement is, I care what lead to it. I would prefer that the report statement contained the instance path(+line number of the code) of the *entity* which lead up to it. Some questions for discussion: * What downsides might there be to such a change? * If implemented, should it be configurable to allow previous behaviour? * Are there times when you actually want the current behaviour? * Would a full traceback (a la Python maybe) be better, or at least a traceback through other calls as far as the entity containing the report? Thanks, Martin -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Oct 10 03:32:15 2014
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