Hi, Accellera is working on a verification effort directed at developing a portable stimulus format. In some ways, this is intended to create inputs for intelligent testbench tools. This is currently a "proposed working group" and allows participation from the general community. When it evolves to being a formal Accellera working group (probably early 2015), it will require Accellera membership at that time. I am currently attending the meetings. Others of you interested in VHDL verification may also wish to attend. For more information see: http://www.accellera.org/activities/proposed_working_groups/ Meetings are on Thursdays at 9 am PDT. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jul 10 10:15:00 2014
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