I am suggesting that evaluating expressions works the same way it does now: subtype/range constraints are ignored and everything is treated as a normal integer (or is it universal_integer?). Subtype/range constraints are considered on assignment or port/parameter association. (Please correct me if I am wrong!) - Ryan -----Original Message----- From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of David Koontz Sent: Thursday, July 10, 2014 3:45 AM To: VHDL IEEE Subject: Re: EXTERNAL: Re: [vhdl-200x] Modular types On 8 Jul 2014, at 6:06 am, ryan.w.hinton@L-3com.com wrote: > The simplest, most obvious solution I see is to (1) let all the arithmetic and other operations use integer and/or universal integer (for literals, I believe) types; and (2) effect the modulus on assignment. What happens when you're simply evaluating expressions? -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jul 10 10:07:05 2014
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