RE: [vhdl-200x] Meeting Reminder: Thursday July 10. 8 am

David:

It seems to me that VHDL, C, and Matlab all *index* their matrices the same way.  They may store them differently in memory (hence they flatten them differently), but indexing is always (row,col) as far as I can tell.

I ported my earlier VHDL example to Matlab.  Here it is along with the printed results.

What is the disconnect between our two understandings?


================ Matlab indexing example code & results =================
>> mat = [1.0, 2.0, 3.0;
       4.0, 5.0, 6.0; 
       7.0, 8.0, 9.0];
>> 
>> for ii=1:size(mat, 1),
  for jj=1:size(mat,2),
    fprintf(1,'%d ', mat(ii,jj));
  end
  fprintf(1,'\n');
end
1 2 3 
4 5 6 
7 8 9 
>> 
>> fprintf(1,'Element (0+1,2+1) is %d.\n', mat(1,3));
Element (0+1,2+1) is 3.


==================== VHDL indexing example results =========================

# 1.000000e+00 2.000000e+00 3.000000e+00 
# 4.000000e+00 5.000000e+00 6.000000e+00 
# 7.000000e+00 8.000000e+00 9.000000e+00 
# 
# So element (0,2) is 3.000000e+00

================== VHDL indexing source code =======================
(copied from 30 Jun 2014 post)



use std.textio.all;

entity multidim_index_order is
end entity multidim_index_order;
architecture a of multidim_index_order is begin

  p: process is
    variable ln : line;
    type REAL_MATRIX is array (natural range <>, natural range <>) of real;
    constant mat : REAL_MATRIX := ((1.0, 2.0, 3.0),
                                   (4.0, 5.0, 6.0),
                                   (7.0, 8.0, 9.0));
  begin
    for ii in mat'range(1) loop
      for jj in mat'range(2) loop
        write(ln, real'image(mat(ii,jj)) & " ");
      end loop;
      writeline(output, ln);
    end loop;
    
    writeline(output, ln);  -- blank line
    write(ln, "Element (0,2) is "&real'image(mat(0,2)));
    writeline(output, ln);
    wait;
  end process p;

end architecture a;




-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of David Bishop
Sent: Thursday, July 10, 2014 7:52 AM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Meeting Reminder: Thursday July 10. 8 am

On 07/10/2014 01:56 AM, Jim Lewis wrote:
> Hi
> _Next Meeting_:   Thursday July 10. 8 am
>
> See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/2014_MeetingJuly10
>
> Jim
>
>
>
>
Will have to miss.   Meetings.   In ECO hell (just got out of timing 
closure hell, this is another layer of hell you have to get through).

Digested list of changes to the matrix packages:



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