The subject states the question. My own opinion is that it should follow in the similar way of 1076.3 and 1164 because it is so integral to mechanism of design within the simulation and synthesis environments. Keeping it separate, by necessity means that at some point in time, it will become out of date to the main LRM until it is revised, or worse still 'withdrawn' (due to lack of WG support?) as is the current situation. It also may generate wider vendor implementation due to the marketing requirement of being able to claim full VHDL LRM compliance. The two remaining derivatives - VHDL-AMS and VITAL - are both complex and self-contained to warrant being separate related standards. What do people think? -- Regards, Brent Hayhoe. Aftonroy Limited Telephone: +44 (0)20-8449-1852 135 Lancaster Road, New Barnet, Mobile: +44 (0)79-6647-2574 Herts., EN4 8AJ, U.K. Email: Brent.Hayhoe@Aftonroy.com Registered Number: 1744190 England. Registered Office: 4th Floor, Imperial House, 15 Kingsway, London, WC2B 6UN, U.K. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu May 15 15:44:56 2014
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