On 15/05/2014 23:44, Brent Hayhoe wrote: > The subject states the question. > > My own opinion is that it should follow in the similar way of 1076.3 > and 1164 because it is so integral to mechanism of design within the > simulation and synthesis environments. > > Keeping it separate, by necessity means that at some point in time, it > will become out of date to the main LRM until it is revised, or worse > still 'withdrawn' (due to lack of WG support?) as is the current > situation. > > It also may generate wider vendor implementation due to the marketing > requirement of being able to claim full VHDL LRM compliance. > > The two remaining derivatives - VHDL-AMS and VITAL - are both complex > and self-contained to warrant being separate related standards. > > What do people think? > I agree that combining the two standards is a good idea as they are an integral part for most users. I don't believe I have ever seen a synthesis tool that claims to be compliant with the 1076.6 standard or even mention it. VHDL-AMS and VITAL should remain separate to keep the LRM lean. VITAL will probably fade away as soon as simulators become dual language out of the box. Regards, Hans. www.ht-lab.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri May 16 01:27:14 2014
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