On 27/03/2014 22:50, Jones, Andy D wrote: > I agree with Jim (why do we need this?), especially if it will be > restricted to a synchronous context (of which vhdl simulators know > nothing). > > If not restricted to synchronous contexts, I abhor the thought of > defining standard attributes for clock, reset, etc. for an implicit > register for a signal (note that current attribute semantics would > not allow such a use model anyway). If I wanted that, I'd still be > using Abel. Agreed. This is completely contrary to the philosopy of the language. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Mar 28 02:14:29 2014
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