Re: EXTERNAL: Re: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

Simulators would be able to simulate the delays. By knowing the clock
period and counting the number of cycles, the simulator would be able to
calculate the amount of delay that is required.

From a synthesis standpoint, tools will infer registers, and do not need to
worry about delays in terms of continuous-time units.

My previous email describes this in more detail.

The purpose of the proposal is to simplify adding pipelines to expressions,
and will find many uses in math-intensive applications, such as DSP. Also,
when performing timing tweaks at the RTL, one could find this useful as
well.

In terms of philosophy, the reason why VHDL is so descriptive is so that
designers can write more behavioural code, rather than hooking up many
structural blocks together (which is one of the goals this proposal is
trying to avoid).

Anyway, I will be consolidating all your comments on the Twiki. Please feel
free to add more if you hold a strong opinion.

-daniel


On 28 March 2014 17:13, Evan Lavelle <eml-vhdl-200x@cyconix.com> wrote:

> On 27/03/2014 22:50, Jones, Andy D wrote:
>
>> I agree with Jim (why do we need this?), especially if it will be
>> restricted to a synchronous context (of which vhdl simulators know
>> nothing).
>>
>> If not restricted to synchronous contexts, I abhor the thought of
>> defining standard attributes for clock, reset, etc. for an implicit
>> register for a signal (note that current attribute semantics would
>> not allow such a use model anyway). If I wanted that, I'd still be
>> using Abel.
>>
>
> Agreed. This is completely contrary to the philosopy of the language.
>
>
>
>
>
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