Hi Srini, > Binding to a physical clk source, describing pipelines - is natively done in PSL as far as I understand. Maybe I am missing something here. Assuming you are writing the concurrent code : Binding can be done with a default clock declaration: default clock is (rising_edge(aClk)) ; qa <= {next[2] d} ; -- uses aClk Or alternately specifying in the SERE: qb <= {next[2] d} @ (rising_edge(bClk)) ; -- uses bClk How would you code reset (both synchronous and asynchronous)? Assume that you can mix SERE with other language syntax. However, if it is used in a clocked process, then we would not want a default clock to apply. This seems potentially problematic. process(Clk)is begin if rising_edge(Clk) then qc <= {next[2] d} ; end if; end process ; Resets may not work the way you want them to. What happens on the transition from reset to clk paths? One clock of 'U'? Reset1Proc : process(Clk, nReset)is begin if not nReset then qc <= '0' ; elsif rising_edge(Clk) then qc <= {next[2] d} ; end if; end process Reset1Proc ; You may need to make sure all assignments have a balanced pipeline. However, with the additional details and opportunities to make mistakes, is this really helping? Reset2Proc : process(Clk, nReset)is begin if not nReset then qc <= {next[2] '0'} ; elsif rising_edge(Clk) then qc <= {next[2] d} ; end if; end process Reset2Proc ; It should be fairly straight forward to sketch out all the potential use models, but it is certainly valuable or we would end up with something odd, like reset1Proc. As a general note, if you code combinational logic separately from flip-flops - ie: if a proposal like this is going to have much meaning to you, then you are probably going to want to use default clock declarations. One of the issues with current code coverage is that for combinational logic, it counts executions from all process executions. What we really want though is to only accumulate statistics from the execution immediately before the default clock. Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Mar 28 00:37:34 2014
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