Daniel, Not sure if this was explored earlier, sorry to jump in late. As you may know, PSL (IEEE 1850) is now integrated into VHDL-08 and offers this natively. So a series of options open-up for this such as: -- Rough syntax, not yet in PSL a <= {next[2] d}; --- i.e. use the "next" family of operators. There are great variants available as part of "SEREs". And the notion of default clock exists and the "@" symbol too. Would the community be open to exploring this? If yes we can spend time in adding more to this proposal. Regards Srini On Thu, Mar 27, 2014 at 11:14 PM, Daniel Kho <daniel.kho@tauhop.com> wrote: > Hello, > For the ClockedShorthand<http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/ClockedShorthand>proposal, it seems that Syntax 1 was generally accepted by most people > during previous discussions. > > However, Syntax 1 proposed two different syntaxes which serve the same > purpose: > Syntax 1a: > q <= d @ 2; > > Syntax 1b: > q <= d after 2; > > where '2' indicates the number of cycles to delay d before effectively > driving q. > > I would like to seek your comments on which of the two syntaxes is more > favourable, and why? > > Or does anyone think that both syntaxes should be supported? > > regards, daniel > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Mar 27 19:33:08 2014
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