RE: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

Le 2014-03-27 20:12, ryan.w.hinton@L-3com.com a écrit :
> True, there is the possibility of confusion. There are a few
> differences, though, between the pipelining "after" and the
> "asynchronous" after. First, the synchronous "after" only works in the
> new clocked process context.

This also raises the question of _which_ clock to use for the delay.
and since "cycle" or "cycles" might be already used as a variable name,
why not use the clock's name as a delay qualifier ?

a <= b after 3 clk;

But I'm not totally satisfied by this,
the word "after" traditionally involves a time delay,
while here we have a different semantic.
The pipelining would be more obvious with
a "delayed" or "pipelined" keyword.
Or something like that.

I don't see how/where I would use this.
But to me, mentioning the clock signal is a step forward.

yg

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