Re: [vhdl-200x] FSM safe design

On Thu, 2014-02-20 at 00:42 +0000, Brent Hayhoe wrote:
> State machine design in VHDL can be performed in quite an elegant manner IMHO. 
> That is using the provision of enumerated types.
> 
> However, there is a problem which some people are still unaware of.
> 
> I remember questioning various vendors about safe FSM design in the late 
> nineties and only one had any sort of provision for it at that time. The 
> situation has since improved.
> 
> The classic VHDL problem is this:
> 
>     type my_fsm is (a, b, c);
> …
>     case my_fsm_signal is
>        when a => if (start = true) then my_fsm_signal <= b; end if;
>        when b => my_fsm_signal <= c;
>        when c => my_fsm_signal <= a;
>     end case;

> Although there are methods of adding synthesis attributes to handle this, it 
> would be nice to incorporate it within the language semantics, e.g;
> 
>      when others safe(my_fsm_signal <= a);
> 
> Has anyone else had any thoughts regarding this issue?

I like the intent, but I wouldn't want to add reserved words or syntax
to the language to handle it. Adding an attribute "safe" or
"full_case_coverage" to the enumerated type and using a plain "when
others" case seems more appropriate. 

Define a standard attribute for the purpose, establish its intent,
(namely, to suppress "redundant clause" optimisations and implement full
coverage. A warning describing the excess resources over "optimal"
solution might be appropriate) Then work with (at least some) tool
vendors to support it, and let peer pressure bring the rest on board.

If there already is a named standard attribute for the purpose, ... then
all I can say is, there isn't enough noise about it yet!

- Brian



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