RE: [vhdl-200x] FSM safe design

Hi Brent,

What I usually do to avoid the warnings is:

    case my_fsm_signal is
       when a => if (start = true) then my_fsm_signal <= b; end if;
       when b => my_fsm_signal <= c;
       when others => my_fsm_signal <= a;
    end case;

In that way, you should be able enforce the tool to make an arc from the non-described D state to the A state.
If for some reason (timing issue e.g.) the state D is reached, but it does not have an ARC, you get stuck in a deadlock.

I do like your idea to handle it in the language, and not in the way you write your case statements, without pragmas/directives/attributes, but in plain VHDL.

Regards,
Jakko


________________________________________
From: owner-vhdl-200x@eda.org [owner-vhdl-200x@eda.org] on behalf of Brent Hayhoe [Brent.Hayhoe@Aftonroy.com]
Sent: 20 February 2014 01:42
To: vhdl-200x@eda.org
Subject: [vhdl-200x] FSM safe design

State machine design in VHDL can be performed in quite an elegant manner IMHO.
That is using the provision of enumerated types.

However, there is a problem which some people are still unaware of.

I remember questioning various vendors about safe FSM design in the late
nineties and only one had any sort of provision for it at that time. The
situation has since improved.

The classic VHDL problem is this:

    type my_fsm is (a, b, c);
…
    case my_fsm_signal is
       when a => if (start = true) then my_fsm_signal <= b; end if;
       when b => my_fsm_signal <= c;
       when c => my_fsm_signal <= a;
    end case;

Given this trivial example, the problem is one of synthesis mapping. Three
states have to be mapped into a minimum of four states and how do you perform
the equivalent of a ‘when others’ catch-all clause to ensure a safe state
machine design.



If you put this clause in the source code, the compiler, quite rightly, will
tell you that it is not required and will be ignored.

Most clients that I have worked for require that all state machines must have
2**x states in order to ensure safe design. This is a solution, but goes against
abstraction design techniques IMHO.

Although there are methods of adding synthesis attributes to handle this, it
would be nice to incorporate it within the language semantics, e.g;

     when others safe(my_fsm_signal <= a);

Has anyone else had any thoughts regarding this issue?

--

Regards,

         Brent Hayhoe.

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