[vhdl-200x] FSM safe design

From: Brent Hayhoe <Brent.Hayhoe@Aftonroy.com>
Date: Wed Feb 19 2014 - 16:42:14 PST
State machine design in VHDL can be performed in quite an elegant manner IMHO. 
That is using the provision of enumerated types.

However, there is a problem which some people are still unaware of.

I remember questioning various vendors about safe FSM design in the late 
nineties and only one had any sort of provision for it at that time. The 
situation has since improved.

The classic VHDL problem is this:

    type my_fsm is (a, b, c);
    case my_fsm_signal is
       when a => if (start = true) then my_fsm_signal <= b; end if;
       when b => my_fsm_signal <= c;
       when c => my_fsm_signal <= a;
    end case;

Given this trivial example, the problem is one of synthesis mapping. Three 
states have to be mapped into a minimum of four states and how do you perform 
the equivalent of a ‘when others’ catch-all clause to ensure a safe state 
machine design.

If you put this clause in the source code, the compiler, quite rightly, will 
tell you that it is not required and will be ignored.

Most clients that I have worked for require that all state machines must have 
2**x states in order to ensure safe design. This is a solution, but goes against 
abstraction design techniques IMHO.

Although there are methods of adding synthesis attributes to handle this, it 
would be nice to incorporate it within the language semantics, e.g;

     when others safe(my_fsm_signal <= a);

Has anyone else had any thoughts regarding this issue?



         Brent Hayhoe.

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Received on Wed Feb 19 16:42:37 2014

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