Hi, One of the things I have wanted is the ability to control VHDL assert statements better. Turn them off until the design is almost out of reset. The ability to stop on errors from numeric_std. One way to address this is to add an API for Assert. I added a proposal for this on TWIKI at: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/AssertApi Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Sep 13 11:53:47 2012
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