Hi, With the current level of integration of PSL, information flows from VHDL to PSL. However, information does not flow from PSL to VHDL. It would be nice to use the coverage accumulated by PSL cover directives to change controls in a testbench. It would be nice to be able to run a process when a sequence, property, assert (fails), or cover (true) occurs. These both are addressed in the Attributes/API for PSL proposal: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/PslAttributes Note, this is a brainstorm level proposal, so I am hoping others jump in and help contribute to this. Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Sep 13 12:05:06 2012
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