RE: [vhdl-200x] conditional compilation proposal

From: Higgs, Chris <>
Date: Tue Aug 16 2011 - 09:31:25 PDT

>> I think it would be helpful if you could expand on some alternative
>> specific use case examples where a pre-processor would be preferable
>> generate which don't involve simply getting rid of unwanted code...

> Here's some output code from a Verilog code generator. It works around
> vendor bugs. Note that these are sequential statements.

If generate were extended to support sequential statements this use case
could be satisfied? Assuming of course that we solve the issue of
allowing "tools to provide information in the form of predefined

function real _$ID23;
input dummy;
`ifdef __EDA_VENDOR_1__
real t;
t = $time;
_$ID23 = t / 1.000000e+00;
`elsif __EDA_VENDOR_2__
reg[63:0] t;
t = $time;
_$ID23 = $itor(t) / 1.000000e+00;
_$ID23 = $time / 1.000000e+00;

Please consider the environment before printing this email.
This message should be regarded as confidential. If you have received this email in error please notify the sender and destroy it immediately.
Statements of intent shall only become binding when confirmed in hard copy by an authorised signatory.
The contents of this email may relate to dealings with other companies under the control of BAE Systems plc details of which can be found at
Detica Limited is a BAE Systems company trading as BAE Systems Detica.
Detica Limited is registered in England and Wales under No: 1337451.
Registered office: Surrey Research Park, Guildford, Surrey, GU2 7YP, England.

This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Tue Aug 16 09:31:49 2011

This archive was generated by hypermail 2.1.8 : Tue Aug 16 2011 - 09:31:55 PDT