RE: [vhdl-200x] conditional compilation proposal

>> I think it would be helpful if you could expand on some alternative
and
>> specific use case examples where a pre-processor would be preferable
to
>> generate which don't involve simply getting rid of unwanted code...

> Here's some output code from a Verilog code generator. It works around
2
> vendor bugs. Note that these are sequential statements.

If generate were extended to support sequential statements this use case
could be satisfied? Assuming of course that we solve the issue of
allowing "tools to provide information in the form of predefined
variables"...

-----------------------------------------------
function real _$ID23;
input dummy;
`ifdef __EDA_VENDOR_1__
real t;
begin
t = $time;
_$ID23 = t / 1.000000e+00;
end
`elsif __EDA_VENDOR_2__
reg[63:0] t;
begin
t = $time;
_$ID23 = $itor(t) / 1.000000e+00;
end
`else
_$ID23 = $time / 1.000000e+00;
`endif
endfunction

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