RE: [vhdl-200x] conditional compilation proposal

The example below would be nicely handled by a generate for the whole
function.

For fine-grained control of statements inside a function, I would use a
standard if statement and allow the compiler to eliminate unused cases. All
you would need is a builtin function like defined("compile_var_name").

--Scott

>
> -----------------------------------------------
> function real _$ID23;
> input dummy;
> `ifdef __EDA_VENDOR_1__
> real t;
> begin
> t = $time;
> _$ID23 = t / 1.000000e+00;
> end
> `elsif __EDA_VENDOR_2__
> reg[63:0] t;
> begin
> t = $time;
> _$ID23 = $itor(t) / 1.000000e+00;
> end
> `else
> _$ID23 = $time / 1.000000e+00;
> `endif
> endfunction
>
>
>
>
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