Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

Jim,
*Yes and VHDL records can easily handle this case, however, the issue
*

> * is: we need to be able to handle a bus where the bus master has
> has 5 Grant line outputs and 5 request line inputs (it would be acceptable
> if either separate std_logic signals or std_logic_vectors) however each
> of the 5 bus slaves has only one grant input and one request output.
> Furthermore, it would be nice if the number of request and grant lines
> are configurable with a parameter/generic.*
>
> [Ben] Interfaces can be parameterized. Also, interface can incorporate
within them other interfaces. I cooked up this simple interface model for a
UART using VHDL.
You may not like my proposed syntax. However, the format is modeled after
SystemVerilog interface.
interface uart_if is
  port(Clk16xT : in bit;
        ResetF : in bit);
     -- internal signals that can be used in the modports
     signal Serial_InT : bit;
     signal DataRdyT : boolean;
     signal DataOuT : Bit_Vector(7 downto 0);
     signal BitClkT : bit;
  -- Can add PSL assertions too
  modport master_if_mp is
    port(Serial_InT : in,
         DataRdyT : out,
         DataOuT : out,
         BitClkT : out);

  modport slave_if_mp is
    port(DataRdyT : in,
         DataOuT : in,
         BitClkT : in);
end interface

>
> * [Ben] I don't think that SystemVerilog interface looks a bit like a
>> class,
>> *
>
> * This thought is not about the current SV implementation -
> instead it is about defining and effective implementation
> in VHDL.*
>
> [Ben] I took the word "class" to mean something like SystemVerilog class,
instead of meaning "category". Sorry.
Ben Cohen SystemVerilog.us
 ===

> Best,
> Jim
>
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> SynthWorks Design Inc. http://www.SynthWorks.com
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>
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