Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

Hi Ben,
> /If the intent is to abstract an interface, then records cannot handle a bus with multiple request and grant lines where each slave interface only drives one request and reads one grant. *I don't
> think SV does either.*/
>
> [Ben] In SystemVerilog you can have interface signals that are wire, and have multiple drivers. Modports allow you to specify which signals are inputs, output, or inout.
> For example: ...
Yes and VHDL records can easily handle this case, however, the issue
is: we need to be able to handle a bus where the bus master has
has 5 Grant line outputs and 5 request line inputs (it would be acceptable
if either separate std_logic signals or std_logic_vectors) however each
of the 5 bus slaves has only one grant input and one request output.
Furthermore, it would be nice if the number of request and grant lines
are configurable with a parameter/generic.

> [Ben] I don't think that SystemVerilog interface looks a bit like a class,
This thought is not about the current SV implementation -
instead it is about defining and effective implementation
in VHDL.

Best,
Jim

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Jim Lewis
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