VHDL Interfaces (was RE: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list)

The fundamental reason that SV interfaces came about was
to address the exploding complexity of connections intra and extra
'chip' if you will.

The other underlying reason was to improve designer productivity by
raising the level of abstraction of the basic Verilog wire/port to an
instantiable 'object' that tools could deal with.

Think about whiteboarding a system on chip.. all those 'arrows'
between blocks. You want to capture that intent as a stand alone
object. Assertions travel along with those objects, to help define
rules/usage/specs and proper utilization of the interface. Modports
are 'customized' views of the interface (kind of a 'subset') Realizing
that interfaces might need/require unique clocking schemes/domains..
the concept of 'clocking blocks' was inserted into SV.

Finally, tools should be able to deal with these interfaces, with no
underlying knowledge of the blocks they connect to. e.g. you can
read SV interfaces in to the synthesis tool, the simulation too, the
property/rule checking tool or the formal too, as standalone objects.

If VHDL could adopt a similar concept.. or cleanly define a VHDL version
of the same, and also delineate the connections to other languages
through said interfaces (e.g. If I could use an SV interface to connect
SV, Verilog, System C or VHDL together) it would be extremely useful.

   -tim

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of ben cohen
Sent: Wednesday, March 09, 2011 10:13 AM
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: Re: [vhdl-200x] VHDL enhancements wish list

Jim,
Yes and VHDL records can easily handle this case, however, the issue
is: we need to be able to handle a bus where the bus master has
has 5 Grant line outputs and 5 request line inputs (it would be acceptable
if either separate std_logic signals or std_logic_vectors) however each
of the 5 bus slaves has only one grant input and one request output.
Furthermore, it would be nice if the number of request and grant lines
are configurable with a parameter/generic.

[Ben] Interfaces can be parameterized. Also, interface can incorporate within them other interfaces. I cooked up this simple interface model for a UART using VHDL.
You may not like my proposed syntax. However, the format is modeled after SystemVerilog interface.
interface uart_if is
  port(Clk16xT : in bit;
        ResetF : in bit);
     -- internal signals that can be used in the modports
     signal Serial_InT : bit;
     signal DataRdyT : boolean;
     signal DataOuT : Bit_Vector(7 downto 0);
     signal BitClkT : bit;
  -- Can add PSL assertions too
  modport master_if_mp is
    port(Serial_InT : in,
         DataRdyT : out,
         DataOuT : out,
         BitClkT : out);

  modport slave_if_mp is
    port(DataRdyT : in,
         DataOuT : in,
         BitClkT : in);
end interface

[Ben] I don't think that SystemVerilog interface looks a bit like a class,
This thought is not about the current SV implementation -
instead it is about defining and effective implementation
in VHDL.
[Ben] I took the word "class" to mean something like SystemVerilog class, instead of meaning "category". Sorry.
Ben Cohen SystemVerilog.us
 ===
Best,
Jim

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Expert VHDL Training for Hardware Design and Verification
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