Re: [vhdl-200x] VHDL enhancements wish list

On 1/03/11 10:41 PM, Martin.J Thompson wrote:
> * Using records on inout pins in some fashion (or is that doable in
> 2008 and I haven't found out how yet?)

We could consider that a port is a structure (record) and is accessed
(connected) through a portmap.

Are you after other ways to make connectivity such as inferred signals
(wires)?

> * Easy efficient external language interface (to Python - ideally I'd
> like to write my whole testbench in Python).

I don't seem to recall that Python is either an ANSI or IEEE standard. This
sounds like a case of 'who bells the cat' and does VHPI for Python, as well
as issues on operating an elaborated model which are outside of the current
scope of the standard. You could get the idea this is a tool domain issue.

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