Re: [vhdl-200x] VHDL enhancements wish list

>>> On 04 March 2011 at 07:42, in message <4D7097E6.8060108@gmail.com>, David
Koontz <diogratia@gmail.com> wrote:
> On 1/03/11 10:41 PM, Martin.J Thompson wrote:
>> * Using records on inout pins in some fashion (or is that doable in
>> 2008 and I haven't found out how yet?)
>
> We could consider that a port is a structure (record) and is accessed
> (connected) through a portmap.

You can, but with non-resolved types it's a non-starter currently. And with resolved types you have to ensure that all the drivers are driving 'Z' (or something similar).

Jim sent me (off-list) his framework for working around this, which involves providing resolution functions for integer etc and defining 0 as a non-driving value. This is good as far as it goes, but feels like a bit of a fudge (no slur intended Jim - it gets the job done with thee tools available!).

>
> Are you after other ways to make connectivity such as inferred signals
> (wires)?
>

No, I'm not keen on inferred-ness in VHDL as a rule.

>> * Easy efficient external language interface (to Python - ideally I'd
>> like to write my whole testbench in Python).
>
> I don't seem to recall that Python is either an ANSI or IEEE standard.

True enough

> This
> sounds like a case of 'who bells the cat' and does VHPI for Python,

'who bells the cat' - I've learned a new idion there :)

I wasn't clear - I don't want this group to "do" VHPI for Python (or any other language/tool).

I would like an *efficient* interface to external tools (mine would be Python) so that they can "run a simulation" cycle-by-cycle (potentially) - it's not clear to me that VHPI currently offers that. If I'm wrong, that's great - I'll just get hacking on a VHPI interface for Python :)

Cheers,
Martin

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