RE: [vhdl-200x] Meeting Reminder: Wednesday January 26 at 8 am Pacific

Hi Jim / vhdl-200x,

Unfortunately I won't be able to dial into the meeting tomorrow. However
I would like to circulate a couple of points I would contribute if able
to attend.

Firstly, I am happy with the minutes from the last meeting.

Secondly, regarding interfacing to other languages I feel it is
important to clarify what we are expecting from additional interfaces to
scripting languages (ignoring the discussion about SystemVerilog/System
C TLM).

What are we expecting that cannot currently be implemented using VHPI?

If there are any deficiencies in VHPI should they not rather be
addressed by improving VHPI rather than creating additional interfaces
(with the associated problems of pushing tool vendors to support them)?

Is it the responsibility of VHDL to support multiple language interfaces
(all of the scripting languages mentioned support some form of C based
interface or extension capability)?

I suspect that much of what is being requested is already possible using
VHPI. For background reading refer to pyHVL
(http://pyhvl.sourceforge.net/) which provides a python interface
through the Verilog PLI. It is possible to do the same thing with VHPI.

Finally, regarding general language change requirements, please consider
hierarchical library/package implementation such that the following VHDL
code is valid:

library mylibrary.sublibrary1.sublibrary2;
use sublibrary2.mypackage.object;

or even better adopt something similar to python by allowing arbitrary
renaming of namespace objects on import:

library this.that.theother as nicename;
use nicename.thingy.footype as foo;
..
signal my_foo : foo;

Thanks,

Chris Higgs

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jim Lewis
Sent: 25 January 2011 04:17
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Meeting Reminder: Wednesday January 26 at 8 am
Pacific

Hi,
Meeting Reminder:
Next Meeting of the VHDL study/working group meeting is
on Wednesday January 26 at 8 am Pacific.

   Dial in 1-800-637-5822
   Intl Access: +1 647-723-3937
   Passcode: 6850837

This meeting is an official IEEE study/working group meeting
and is governed by the IEEE patent policy. Please read the
following before the meeting:
 
https://development.standards.ieee.org/myproject/Public/mytools/mob/slid
eset.pdf

Initial Agenda:
   Review Meeting Minutes from Last Meeting
 
http://www.eda-twiki.org/vasg/meetings/2011_0110_meeting_minutes_unofficial.tx
t

   Discuss WG P&Ps
     As homework before the meeting, please review the IEEE WG P&Ps &
suggest
     customizations (where allowed) for our WG:
       http://standards.ieee.org/about/sasb/audcom/wg_pp_0110.doc

     You can also find this document by following the link from this
page:
       http://standards.ieee.org/about/sasb/audcom/bops.html

   Initiate discussion of language change requirements
     - it will expedite things if you come with a list
       for discussion

   Proposed Next Meeting Date: Thursday Feb 10 at 8 am Pacific

Best,
Jim Lewis
VHDL Study Group Chair

If you are reading this on the website and wish to receive these
via email, see the following link to sign-up for the reflector:
    http://www.eda-twiki.org/vasg/index.html#Participation

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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