Re: [vhdl-200x] 1076 Working Group Par Vote

Jim,
My 2 cents on the issues below:
*Victor also requested that the study group further elaborate*
*on the purpose of the revision/PAR. To address this, I
requested that the study group to further elaborate
on the purpose to the par and specifically:
   What is intended by Verification enhancements?
    1) Create an API/interface/package that allows interfacing
       VHDL to SystemC and/or SystemVerilog/UVM
       vs
    2) It could also mean we implement full OO and UVM-like
       stuff in VHDL.*
[Ben] I am strongly in favor of option 1 because:
  - OO is already built into SystemVerilog, and reinventing the wheel is too
time consuming for this group, and is too expensive for tool vendors who
already have SystemVerilog and SystemVerilog/VHDL tool solutions. In
addition, VMM/OVM/UVM frameworks are already written, and have maturity.
 You don't want to rewrite them into VHDL.

*There are many in the study group who believe that creation of
direct C interface is a worthy task to do.
The study group had mixed opinions on things like OO/classes,
data structures (syntax or package based), functional coverage,
constrained random, and/or interfaces, so the
1076 working group will need to trade-off/explore what
to do about these if anything.*
[Ben] The PI/interface/package that allows interfacing VHDL to SystemC
and/or SystemVerilog/UVM will provide for all these features at a very low
cost for implementers.
In fact, the Binding SystemVerilog to VHDL components (with SV bind) is
already implemented by vendors; however, taht feature is not in the
SystemVerilog or VHDL LRM.
Ben Cohen Ben@systemverilog.us

On Thu, Jan 6, 2011 at 1:01 AM, Jim Lewis <Jim@synthworks.com> wrote:

> Hi,
> This is to document the results of the VHDL/1076 study group
> vote on group organization and the PAR.
>
> Item 1: Working group organization.
> Total votes:
> 26 Individual
> 5 Corporate
> 3 Abstain
>
> Item 2: 1076 PAR.
> http://www.eda-twiki.org/vasg/p1076_2014_draft_par.pdf
> Total votes:
> 31 Approve
> 1 Negative
> 2 Abstain
>
> The study group has approved the working group to be
> individual based membership and approved the PAR.
> Detailed voting records are here:
> http://www.eda-twiki.org/vasg/voting/110105_PAR_VOTE.pdf
>
>
> ---------
>
> Victor also requested that the study group further elaborate
> on the purpose of the revision/PAR. To address this, I
> requested that the study group to further elaborate
> on the purpose to the par and specifically:
> What is intended by Verification enhancements?
> 1) Create an API/interface/package that allows interfacing
> VHDL to SystemC and/or SystemVerilog/UVM
> vs
> 2) It could also mean we implement full OO and UVM-like
> stuff in VHDL.
>
> This email is at: http://www.eda-twiki.org/vhdl-200x/hm/1091.html
>
> There are many in the study group who believe that creation of
> direct C interface is a worthy task to do.
> The study group had mixed opinions on things like OO/classes,
> data structures (syntax or package based), functional coverage,
> constrained random, and/or interfaces, so the
> 1076 working group will need to trade-off/explore what
> to do about these if anything.
>
> Best Regards,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> --
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