Re: [vhdl-200x] Request for Input

On Fri, Dec 31, 2010 at 6:22 PM, David Bishop <dbishop@eda.org> wrote:

> Maybe a built in operator?
>
> Z <= x**2/y @ 15;

Well, maybe. Which clock, though?

Verilog already has elegant syntax and appropriate semantics
to express this idea (pipelining):

  Z <= repeat 15 @(posedge clock) some_expression;

but, to their undying shame, none of the synth tools allow that syntax.
It is a brilliant way to describe pipeline delay without specifying the
fine details of precisely where registers should go in the logic.

You could vaguely imagine such a thing in VHDL:

  Z <= transport some_expression after pipeline_delay;

but what do you do for pipeline_delay? VHDL lacks
concise "repeat" syntax; the for-loop syntax is way too
clumsy. Better to use a PSL temporal expression:
I think this is exactly what you want. PSL is now
built-in to VHDL-2008, right?

  Z <= prev(some_expression, 15, rising_edge(clock));

But that takes us into other territory - specifically, the whole area
of synthesising logic from the temporal syntax of an assertion
language. It's not crazy, but I'm not aware of any existing
commercially-available examples.

Maybe, given the semantic equivalence between these
existing syntactic forms in Verilog and VHDL, someone
could put some pressure on synth tool vendors to support
that syntax? All self-respecting synth tools now have at
least some idea of pushing registers through logic, so
it shouldn't be too hard for them to support it. And it
means NO NEW LANGUAGE FEATURES, which
I've already argued is a must for VHDL today.

Jonathan Bromley

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