Re: [vhdl-200x] Request for Input

With apologies for replying to myself, a correction:

[Verilog]
>  Z <= repeat 15 @(posedge clock) some_expression;
[VHDL]
>  Z <= prev(some_expression, 15, rising_edge(clock));

> Maybe, given the semantic equivalence between these
> existing syntactic forms in Verilog and VHDL

oops, not quite. Both are a reasonable description of
pipelining, but their semantics are different because the
Verilog version does not update Z at all until 15 clocks
have elapsed, whereas the PSL form updates Z
after only one delta, but possibly (at the start of simulation)
with a garbage value because there is no past(...).

An alternative Verilog form, genuinely equivalent to the PSL:

  Z <= $past(some_expression, 15, @(posedge clock));

Jonathan Bromley

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