Re: [vhdl-200x] Request for Input

On 12/31/2010 1:12 AM, Daniel Kho wrote:
> I would really like to stick to the "function" way of describing this,
> as it is much less verbose, though I would also like to have a way for
> functions to be able to be clocked. So, in my design, I can just stick
> to something like:
> z <= x**2 / y; --where "/" is an internal function (I think it's in
> the std library - not too sure)
> instead of writing:
> q<=x**2;
> divider0: entity work.div32(rtl) port map(a=>q, b=>y, res=>z,
> remainder=>remainder);
>

I see the problem here. There are several practical ways to do a
divider, and several unpractical ones as well. I will usually create a
custom divider for any project that needs one once I figure out what the
constraints are. It would be cool to quantify what those are and make
an attribute (like Synopsys sometimes does it), but a more generic
solution would be better. You think that multipliers are tough for
Formal verification tools? Think about a divider... I get around
this by using pretty much the same solution you have come up with.

With a multiplier, there are far fewer ways to do it, but they all boil
down to faster or smaller, so I typically trust the synthesis tool to
pick the right one. With dividers, current synthesis tools don't have
the brains to do this.

What most "pricier" synthesis tools can do is to move FFs back into a
function, but it is usually a feature you have to not only turn on, but
pay a premium for.

First thing I would think of would be a "Z transform", which is
basically a delay stage, but that still make you use an entity.

> function "/"({parameter_list})
> begin
> return entityName.architectureName.processName({parameter_list});
> end function "/";

Cool idea, but how do you pass a clock to it?

I think that something like:
function zt ( var : <some type>
clock: std_ulogic;
reset: std_ulogic;
delay: Positive := 1;
enable: std_ulogic : ='1')
return <some type>;
might work. Might be something to play with.

The hope would be to let the synthesis tool figure out the divider style
(given some constraints) and move the FFs back into the divider until
timing is met.

Maybe a attribute to set a default clock, reset and enable? Then it
would look like:

Z'default_clock := clk;
Z'default_reset := rst;
Z'default_enable := '1';

Z : zt (x**2 / y, 15);

Maybe a built in operator?

Z <= x**2/y @ 15;

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