>>> On 20 December 2010 at 15:20, in message
<6AB841E80B324E2A8AE06CF5D99D2ECA@linux104>, "Hans" <hans64@ht-lab.com>
wrote:
> I don't understand Jonathan's idea to make an easy interface to other
> language
> since most simulators already provide this. In my case (I use Modelsim) it
> is
> very easy to add a SystemC testbench to my VHDL code or to use the DPI
> interface
> via a thin SV layer, standardizing this is not going to make any difference
> to
> me.
I'd rather not use anything C based for verification - can I easily use Python (for example) with Modelsim? Preferably without buying the "vastly-expensive-edition" license?
>
> I do however like Jonathan's idea of "leapfrogging SV", not sure how but
> something to think about.
I think *only* by using an external language. Anything that takes VHDL even close to SV will take so long to be implemented by the EDA vendors as to be useless. Whether even a tight, well-defined external interface can be pushed along any more quickly remains to be seen... maybe VHDL needs an open-source competitor to the big EDA tools?
Cheers,
Martin
-- Martin Thompson CEng MIET TRW Conekt, Stratford Road, Solihull, B90 4GW. UK +44 (0)121-627-3569 : martin.j.thompson@trw.com http://www.conekt.co.uk/ Conekt is a trading division of TRW Limited Registered in England, No. 872948 Registered Office Address: Stratford Road, Solihull B90 4AX -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Dec 20 07:49:36 2010
This archive was generated by hypermail 2.1.8 : Mon Dec 20 2010 - 07:49:38 PST