Reminder, Vote closes 5pm US-PDT, Thursday 12 January, 2006. Regards, Jim ======================================== Dear colleagues, This is a call for vote from IEEE P1076 WG members on the next group of ISAC issues listed below. The ISAC has analyzed the issues and made recommendations for interpretation of the IEEE 1076-2002 standard and for future revisions of the standard. This vote is for approval of the ISAC recommendations. Please note that, in some cases, a recommendation may be to reject a request. In that case, a vote to approve the recommendation means rejecting the request, whereas a negative vote means reconsidering the request. Please take care with the logical sense of your vote in such cases. Also note that some of the issues do not specify detailed LRM edits to implement a change. The intention is that the detailed changes be specified in a Language Change Specification (LCS) document that will be voted on separately. The intent of this vote is to determine whether such an LCS is required. Only votes of eligible voters will be counted. Votes from ineligible voters will be recorded for information and for adding to your "last 2 or 3" participation count. I will acknowledge each vote received and indicate whether it was counted or not. Please forward votes to me by email (eg, by replying to this message) by 5pm US-PDT, Thursday 12 January, 2006. For each issue, would you please vote one of: approve, negative with comments, negative with no comments, or abstain. You may also provide informative comments with a vote to approve a recommendation. Please use the form below. Thank you. Regards, Jim Lewis P1076 Chair Issue Approve Negative Negative Abstain with comment no comment 2028 Clarify simulation cycle. http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2028.txt 2028 ____ ____ ____ ____ Comment: 2043 Numeric VALUE attribute parameter can't have sign http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2043.txt 2043 ____ ____ ____ ____ Comment: 2050 Definition of S'Last_Value was apparently broken in 1993 http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2050.txt 2050 ____ ____ ____ ____ Comment: 2062 Range staticness http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2062.txt 2062 ____ ____ ____ ____ Comment: 2064 Type conversion of unconstrained output in a port map http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2064.txt 2064 ____ ____ ____ ____ Comment: 2065 OTHERS in aggregates too restrictive http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2065.txt 2065 ____ ____ ____ ____ Comment: 2068 Entity instantiation with space before the entity name http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2068.txt 2068 ____ ____ ____ ____ Comment: 2069 Visibility of generics in block configurations http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2069.txt 2069 ____ ____ ____ ____ Comment: 2071 Indexed name in case expression http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2071.txt 2071 ____ ____ ____ ____ Comment: -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Tue Jan 10 09:14:04 2006
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