Steve, Some explanatory notes re your comments on IR2028: In the case of initialization, there may be force or deposit updates scheduled from a previous VHPI call. The only way to get back to initialization after that is to do a reset, in which case scheduled forces and deposits are discarded. In the case of the simulation cycle, scheduled forces and deposits are applied as part of driver and signal update. The scheduling referred to is not for a specific time, but for the next update phase after the call to the vhpi_put_value function. Once the update is performed, the scheduled force or deposit should no longer be scheduled. This is all defined in the draft LRM in clauses 12.6.2 and 20.4.2. Without reference to those clauses, the excerpt in the LRM probably doesn't make a lot of sense in isolation. Hope this clarifies things. Cheers, PA -- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 VoIP: 0871270078@sip.internode.on.net Stirling, SA 5152 Phone (mobile): +61 414 709 106 Australia > -----Original Message----- > From: owner-vhdl-200x@eda.org > [mailto:owner-vhdl-200x@eda.org] On Behalf Of Bailey, Stephen > Sent: Wednesday, 28 December 2005 15:43 > To: Jim Lewis; VHDL-200x > Subject: RE: [vhdl-200x] Call for Vote on Additional Issues > > > Here are my votes. > > -Steve Bailey > > > Issue Approve Negative Negative Abstain > > with comment no comment > > > > 2028 Clarify simulation cycle. > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2028.txt > > 2028 ____ ____ ____ ____ > > Negative with comment > The proposed resolution seems fine except for one issue which > in my mind is significant. The following sentence is used > multiple times: "If a force or deposit was scheduled for any > driver/signal, the force or deposit is no longer scheduled > for the driver/signal." > > I have no clue what this sentence means. If I take it at > face value, it seems that any force or deposit is simply > discarded and not applied. However, I doubt that that is what > is intended. Until this sentence is properly > defined/specified or somehow explained as to its meaning, I > cannot vote positive. > > > 2043 Numeric VALUE attribute parameter can't have sign > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2043.txt > > 2043 ____ ____ ____ ____ > > > Positive > > > 2050 Definition of S'Last_Value was apparently broken in 1993 > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2050.txt > > 2050 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2062 Range staticness > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2062.txt > > 2062 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2064 Type conversion of unconstrained output in a port map > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2064.txt > > 2064 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2065 OTHERS in aggregates too restrictive > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2065.txt > > 2065 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2068 Entity instantiation with space before the entity name > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2068.txt > > 2068 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2069 Visibility of generics in block configurations > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2069.txt > > 2069 ____ ____ ____ ____ > > > > Comment: > Positive > > > 2071 Indexed name in case expression > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2071.txt > > 2071 ____ ____ ____ ____ > > > > Comment: > Positive > > -Steve Bailey >Received on Tue Dec 27 23:23:12 2005
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