All, Kevin brought up a point regarding the 1076.6-1999 (the original 1076.6). I worked on both versions of 1076.6 (1999 and 2004). 1076.6 is intended to standardize the RTL subset for two different parties, IP developers and Synthesis Tool vendors. 1076.6-1999 standardizes a minimal RTL subset so that if an IP developer codes using it, it should work on all existing synthesis tools. 1076.6-2004 gives us a full RTL synthesis subset including leading edge things like multi-clock registers and multi-clock, multi-port memories. As a user if you want less trouble with your design process, request VHDL-IP that is 1076.6-1999 compliant and request synthesis tools that are 1076.6-2004 compliant. Kevin brought up frustration with EDA vendor support of standards. I share this frustration. I respect the fact that EDA vendors run a business and everything they do is an investment. I understand the need to only support features that their users truely need. However we need a situation where users and vendors proactively interact. Perhaps Accellera will provide a step in this direction. I think the next step for 1076.6-2004 is to get a group of people to write testcases and ask vendors to self certify that they support the testcases. While this will not certify compilance, it does give us a metric to quantify what type of tool support we have and gives us something to use as a guide for requesting additional tool support. At that point we will be able to access the market relevance of 1076.6-2004. Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Thu Jul 7 12:17:46 2005
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