RE: [vhdl-200x] Announcement

Steve:

First, I applaud Accellera's new initiative regarding VHDL WG.
It is good to know that the VHDL will be "groomed" as it deserves.

DASC, by not holding a plenary for more than 3 years, with its
SC killing WGs at a fast pace (mostly to reduce the number of voting members 
and be able to make quorum), without a clear view of what is needed,
and its now notorious reluctance to facilitate technical discussions, looks
like it will fade away. 
However, there is effort to correct the lack of technical discussions
with the DATC (thanks Dr. Barton) proposed series of workshops. 
DASC members are invited to strategise about what are the challenges 
to be solved by the standards community, and that is possible without 
joining an expensive organization. Based on those good news I will not 
discard DASC at this time.
There is a second possibility, and that was presented by Mr. Berman, that 
is to make DASC the center of the EDA standards again, by framing it 
accordingly (maybe somehow like the CAG). This perspective will not replace 
Accellera efforts. It will just make a single point for EDA standards efforts in 
the IEEE. 

As IEC US Technical Adviser for DA standards (TC93) and convener of the TC93 
WG2 (HDLs), I represent the interest of keeping a simple procedure for the 
maintenance of Dual Logo (DL) standards (both VHDL and Verilog as many others 
are now DL IEEE/IEC Stds). With work done in Accellera, the IEEE as DASC, 
CAG or a combination of them, it is really hard to follow the agreed maintenance 
procedures. So far the new revision of Verilog was not done according 
to agreed (IEEE-IEC) procedures (no invitation to review, no draft circulated 
in IEC so far). Note also that IEC has the right to maintain the international 
standards on its own, if not "well factored" into the process. We have to work 
more in keeping with procedures that will guarantee international approval for 
whatever comes out of the main work. 

The good quality of IEEE and IEC standards comes mainly from individual 
review during balloting.  With actual setup for VHDL (Accellera will return the 
work to IEEE) it is not guaranteed that individual reviewers will have any voice 
in balloting. I hope that individuals will continue to be able to contribute without 
expensive membership requirements. 

In conclusion:

1. Accellera VHDL initiative looks like good news
2. (IMHO) DASC should not be discarded yet
3. Please help keep simple the IEEE-IEC procedures for DL (and apply/observe them)
    (i.e. re-organization of DASC as the only center for DA standards in the IEEE)
4. Individual participation should not be discouraged

Kindest regards,

Alex Z




-- 
Alex Zamfirescu
azro@onebox.com - email
(877) 332-0676 - voicemail/fax




-----Original Message-----
From:     Bailey, Stephen <SBailey@model.com>
Sent:     Tue, 5 Jul 2005 13:35:07 -0700
To:       <vhdl-200x@eda.org>
Subject:  [vhdl-200x] Announcement

All,

At its Board of Directors meeting at DAC, Accellera approved the
formation of a working group for VHDL.  The IEEE has provided Accellera
permission to create derivative works based on 1076 as long as the
derivative works are submitted back to the IEEE for standardization.

First, I cannot overstate why I believe this development is good for
VHDL.  Accellera approved the VHDL working group only after end-user
companies, specifically Nokia, IBM and Rockwell Collins, stepped forward
and demonstrated that the future of VHDL is important to them.  IBM was
already a full Accellera member and has a seat on the Accellera Board of
Directors.  Nokia and Rockwell Collins have both joined Accellera as
full members and also have seats on the Board of Directors.  In
addition, Xilinx has also expressed an intent to join Accellera as an
associate member very soon.

I have been deeply involved in VHDL standardization since 1989/1990.  We
have always wanted, yet somehow never quite achieved, significant
support and participation from the VHDL user community.  I believe these
developments are finally accomplishing that goal.

Lance Thompson of IBM will be chairing the Accellera working group.  An
announcement for the 1st meeting was distributed to the Accellera
membership last Friday.  I have copied that announcement below.

We will be defining how the IEEE and Accellera WGs will work
cooperatively moving forward over the next few weeks.  However, I expect
the majority of new initiatives to be undertaken within Accellera where
the priorities of the VHDL users will have significant influence.  Once
the technical work achieves a level of stability and completeness, it
will be handed off to the IEEE 1076 WG for further analysis and
standardization.  The existing "fast-track" proposals and VHPI work will
be considered within the Accellera WG.  These efforts are at various
levels of completeness and their value to end users and effort to
complete will be part of the prioritization of the Accellera WG's
activities.  (This WG would need to provide some combination of
volunteer and for-fee LRM writing in order to get them to the point of
ready to ballot.  The benefit of corporate support of VHDL enhancement
and revision work is the ability to provide manpower and funds for this
work.)

--------- Lance Thompson's Invitation to participate:

Invitation to join Accellera VHDL Working Group 

Greetings, 

Accellera would like to invite you to participate in the newly formed
VHDL Working Group. Your VHDL Working Group will be focused on
enhancements to VHDL that you feel will make a difference in your
business. You can join today by visiting
http://www.accellera.org/activities/vhdl. After you join, you can
register with the e-mail reflector to stay connected to our community. 

We are doing two things to get the ball rolling. First, we would like to
invite technology donations from the community. This call for donations
will be open from now until 31 August 2005. If you have technology that
you feel is relevant to the evolution of VHDL, please consider donating
to this working group. If you previously made a technology donation to
the IEEE for its work on VHDL, we ask that you make the same donation to
this working group. 

Second, we have set up an initial meeting. A teleconference will be held
on 14 July 2005 starting at 10:00 am CDT and going until 3:00 pm CDT. If
you like, I have the option of hosting you at the IBM location in
Rochester, MN. An agenda will be published later will contain the
teleconference number as well as the meeting room information. 

One agenda item will require a little homework for those of you that
join us. In order to hit the ground running, the homework is this: send
me your language enhancement priorities before 7 July 2005, so that I
can sort through them and present them at the teleconference. To start
the process, here are IBM's initial priorities: PSL integration into
VHDL, designer productivity enhancements, reading cross hierarchical
signals. During the teleconference, we'll "go around the room" to invite
additional language enhancement priorities. Hopefully, our collective
lists will stimulate other participants. The web site will contains
links that you can browse of some of the many language enhancement
proposals of the recent past. 

We'll have updates on two groups of activities that are currently under
the IEEE. The first is a group of enhancements call the "fast track."
Volunteers for the IEEE have done an excellent job working through
these. For a preview, take a look at http://www.eda-twiki.org/vhdl_200x. In
addition, you'll find
http://www.eda-twiki.org/vhdl-200x/docs/minutes/feb_03_wg_mtg1_rev3.ppt and
http://www.eda-twiki.org/vhdl-200x/vhdl-200x-ft/ particularly interesting. The
second update will be on the progress of the vhpi standard work that has
been going on. The purpose of these updates is to familiarize everyone
with the technical work that has already been done and to consider them
in the context of this working groups priorities. 

Then we'll see if we can turn the meeting into a workshop. During the
workshop, we'll be organizing and making assignments to move our
priorities forward. We should be able to identify the language
enhancements that we would find the most valuable and commit to moving
those enhancements forward. We'll also take a moment to schedule some
future teleconferences and a face-to-face meeting or two. 

I look forward to welcoming you into the group! 

Best regards, 
Lance Thompson 
Accellera VHDL Working Group Chairman 
Senior Engineer 
Engineering & Technology Services 
IBM
 ------ END INVITATION

------------
Stephen Bailey
Product Marketing Manager, ModelSim
Mentor Graphics
sbailey@model.com
303-775-1655 (mobile, preferred)
720-494-1202 (office)
www.model.com