RE: [vhdl-200x] Draft PAR

Steve and colleagues,

Thanks to Steve for preparing the draft PAR. I echo Edward's reservations
about mixed individual/entity balloting. Providing entity voting as a form
of recognition of support doesn't really give any benefit to entities.
Compare that with entity-only balloting, where entities are on the
proverbial level playing field. I think that is perceived as being of
higher value to entities, and would be more likely to attract funding.

An important point to note is that if the ballot group and WG are
entity-based, the WG can still determine separate voting rules for
subgroups, such as technical teams. Those subgroup rules can admit of
individual voting. This might be a way of satisfying people's concerns
about disenfranchisement of individuals in the technical work.

Cheers,

PA
(as a VASG member)

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
Stirling, SA 5152                            Fax: +61 8 8339 2616
Australia                                    Mobile: +61 414 70 9106
> -----Original Message-----
> From: owner-vhdl-200x@eda.org 
> [mailto:owner-vhdl-200x@eda.org] On Behalf Of Bailey, Stephen
> Sent: Thursday, 10 June 2004 16:05
> To: vhdl-200x@eda.org
> Subject: [vhdl-200x] Draft PAR
> 
> 
> Attached is a draft of the PAR.  Peter Ashenden (DASC Chair) 
> has already performed one review cycle and the attached 
> includes comments from his review.
> 
> Note that I'm suggesting that we allow both individual expert 
> and organization entity membership for the working group.  
> The membership of the WG needs to be discussed.  But, here's 
> my thinking as well as an observation from Edward Rashba of 
> iEEE SA on the options here:
> 
> 1.  We need to find financial support for the VHDL-200x work. 
>  Primarily the funds are needed for the focussed effort of 
> editing the VHDL LRM.  I have received estimates for the 
> costs of this work of ~$200k over the course of 2-3 years 
> (two revisions of VHDL under VHDL-200x).
> 
> 2.  I have been informed that Accellera has spent at least 
> $150k to get the SystemVerilog 3.1a LRM to its current state 
> with possibility that a bit more funding will be needed to 
> complete the IEEE standardization process.  Therefore, the 
> estimates for VHDL are within the general ballpark given the 
> expected scope of LRM editing anticipated.  Hopefully, no one 
> should expect that VHDL can do this work at a significant 
> discount to that which was needed for SystemVerilog.
> 
> 3.  Corporate support of our work as expressed by funding for 
> the effort is a great indication that we are doing something 
> that users need (and EDA vendors recognize users want).  
> Therefore, funding is a positive and we should be soliciting it.
> 
> 4.  Therefore, I thought that we could allow both membership 
> classes for 1076.  Although it has not been officially placed 
> to a vote of the WG, I heard feedback that the current 
> members wanted to stay with individual membership.  Allowing 
> organizational entity membership would allow us to also 
> recognize corporate support for our work by giving supporters 
> a direct voice in the WG.
> 
> 5.  Edward Rashba counseled against having both membership 
> classes.  However, he also indicated that in some cases, such 
> as ours, it has and could work.  Our historical operation 
> makes it reasonable to believe that supporting both 
> membership classes for 1076 could work.
> 
> 6.  Personally, I believe individual only membership would 
> hinder the ability of the WG to successfully solicit 
> financial support.  However, I will do my best to find the 
> funding whatever membership option the WG decides to use.
> 
> Since <24 hours is insufficient time to review a PAR and 
> comment, no vote to approve the PAR will be held tomorrow (10 
> Jun 04 Meeting).  However, we will entertain discussion on 
> the topic in preparation for a future vote via email to be 
> conducted in ~2 weeks time.  (Discussion via email is also welcome.)
> 
> I'm looking forward to the meeting.  I think that Erich's 
> work on defining how PSL can be incorporated in VHDL by 
> reference combined with the VHPI and other language change 
> proposals that appear ready to go will result in a new 
> revision that is highly valuable.  It will also lay the 
> foundation for even more capabilities in the next revision.
> 
> To review the proposals visit 
> www.eda.org/vhdl-200x/vhdl-200x-ft 
<www.eda.org/vhdl-200x/vhdl-200x-ft> 
 <<tmp113842779_9644.html>> 
------------
Stephen Bailey
ModelSim Verification TME
Mentor Graphics
sbailey@model.com
303-775-1655 (mobile, preferred)
720-494-1202 (office)
www.model.com <www.model.com>