Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Bailey, Stephen (SBailey@model.com)
Date: Tue Dec 23 2003 - 14:34:24 PST
Tim,
> I don't agree that it is ok for the VHDL
> language to be
> narrow minded. Hardware is described in many ways and fixing the type
> equivalence to the one above would be bad in my oppinion.
The proposal does not "fix" (i.e., hardcode within the language semantics) the boolean equivalence. It provides a way in which the boolean equivalence can be defined. We furthermore are proposing that specific boolean equivalences be predefined in a package for anyone to use. However, anyone would be able to change that definition if the equivalence definitions provided in that package did not match their definition. (If they don't want any equivalence defined, then don't use the package.)
-Steve Bailey
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