Subject: Re: [vhdl-200x] Boolean Interpretation of Std_ulogic
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Tue Dec 23 2003 - 14:34:17 PST
VhdlCohen@aol.com wrote:
> In PSL, Interpreting std_ulogic as Boolean is really for readability,
> and not just to reduce typing. For example:
> ENGLISH: If signal /hit/ is active and signal /pending/ is not, then
> next time /pending/ is active, signal /sel5/ is active.
>
> * property *HitPendingSel5 is *always *{hit and not pending;
> pending[->1]} |-> {sel5};
>
> Note how this description is close to the English description. Also
> note that in English, the property is NOT typically expressed as
>
> "If signal /hit/ is ONE is active and signal /pending/ is ZERO, then
> next time /pending/ is is ONE, signal /sel5/ is ONE.
I agree that it's more readable. However, it doesn't define what active
means. It's assumed to be when the signal is '1' (or 'H', etc). Thus I
would prefer to specify what active means rather than have the language
assume it.
I can see merit in Tim Davis' proposal as an alternate way to solve this
(ie give us a way to define the boolean mapping). Then you get the
readability benefit as well.
> Which do you think is more readable:
>
> *property *HitPendingSel5 is *always *{hit and not pending;
> pending[->1]} |-> {sel5};
>
> or
>
> *property *HitPendingSel5 is *always *{hit='1' and pending='0';
> pending='1'[->1]} |-> {sel5=='1'}; (also legal PSL, by the way)
I prefer the second because there are no unstated assumptions.
Regards,
Hamish
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