Subject: RE: [vhdl-200x] An alternative proposal to boolean equivalence
From: Bailey, Stephen (SBailey@model.com)
Date: Sun Dec 21 2003 - 09:21:16 PST
For PSL information, see the Accellera website (www.accellera.org).
Unless we reinvent the wheel (which we do not have time or resources for), our choices of (emerging) standard property specification languages comes down to:
- PSL
- SystemVerilog Assertions
Since PSL was designed to be HDL neutral, it makes for a better choice for VHDL. Also, it looks like PSL is getting off to a nice start in the market place (people are already using it and multiple vendors already support it).
Your analogy of stucco vs. stone falls apart in that there's no question as to whether or not both will remain available as building choices in the future. I'm not trying to be alarmist, but any objective analysis of the HDL market indicates that Verilog has key leadership over VHDL. The enhancements that are SystemVerilog threaten to eliminate any meaningful advantages of VHDL over Verilog and will actually create meangingful advantages for SystemVerilog.
I know for a certain group of VHDL users, ANY enhancement to Verilog (i.e., SystemVerilog) will never make the cut. Unfortunately, there is real concern that the size of that group of users will be irrelevant from a market perspective. Would that mean VHDL and VHDL tools go away in a couple of years? No. But it does mean VHDL and corresponding tool support would not grow and evolve.
For those who are concerned that we are consumed by "mice snot" with the boolean equivalence proposal in the larger picture, my response is that out-of-context, it is mice snot. In full context, it is an important aspect of gaining a high quality property specification capability with minimal effort on the part of the VHDL WG. (Do you think using SystemVerilog Assertions would eliminate the need for this proposal? No.)
We are also working on more far-reaching language changes with corresponding increases in benefits for users. However, those changes fall outside the scope of the fast-track team and will take longer to mature. But, you will be seeing proposals for them over the next 12-18 months.
-Steve Bailey
> -----Original Message-----
> From: Munden Rick [mailto:Rick.Munden@Siemens.com]
> Sent: Friday, December 19, 2003 9:00 PM
> To: Bailey, Stephen
> Cc: 'Evan Lavelle'; VHDL-200x
> Subject: Re: [vhdl-200x] An alternative proposal to boolean
> equivalence
>
>
> Steve,
>
> I don't think people are trying to say anything that is like
> verilog is
> bad. I think their point is we have two languages that are
> different.
> They (can) serve different needs. We can build using stone
> or stucco.
> Which is better? It depends on our needs. Stone lasts longer but is
> more expensive and slower. Often, we only need to build for
> the short
> term. Why would we want to use stone? Other times we want
> to build for
> the long term. The extra time and expense is justified. Then we use
> stone.
>
> For the work I do, which is not synthesis, a restrictive, verbose,
> strongly typed language is ideal. That is not the case for
> everyone and
> thats OK. That is why, at the end of the so called language
> wars, there
> were still two languages.
>
> My understanding is that the boolean equivalence issue came
> up because
> of PSL. I would like to understand that issue better. What are the
> requirements and is there another approach to meeting them?
> I have not
> had time to look this up on the website. Is there something
> there to study?
>
> Thanks,
> Rick
>
>
> Bailey, Stephen wrote:
> >>Equality is trickier: do you want to handle don't cares? Is that a
> >>proposal? It could be handled in the same way as the
> >>case(x/z) statement
> >>when the operands are of type 'logic', but this would be
> incompatible
> >>with Verilog. Not a problem, but it would be nice to be compatible.
> >
> >
> > Yes, there will be a proposal on how to handle don't care.
> But, we'll discuss that when it is ready.
> >
> > It is nice to see that when the context changes, Verilog is
> now something to be emulated. Point being: let's stop using
> Verilog as an ad hominem attack against proposals. Judge the
> proposals on their merits.
> >
> > Thanks,
> >
> > -Steve Bailey
>
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