Subject: RE: [vhdl-200x] An alternative proposal to boolean equivalence
From: Robert Ingham (robert.ingham@candc.co.uk)
Date: Mon Dec 22 2003 - 02:57:09 PST
[The server originally rejected this, so I am reposting. I fear that the server may be overloaded by spam - overloaded in a non-VHDL sense, of course :)]
1. We are in danger of generating more heat than light on this issue, but
isn't it nice that people care?
2. I would like to see explicit 'to_boolean' functions in a/the standard.
The issue regarding std_logic meta-values can be dealt with in a similar way
to that in the 'numeric_std' package, with them mapping to 'false', and (in
simulation at least) a warning message being issued - or is that
tool-specific? We will have to be aware, and make well-known, that the
expressions:
not to_boolean(slv_signal)
and
to_boolean(not slv_signal)
are not equivalent.
3. From that, any implicit type conversion (whether through overloading of
'if' etc.) that is required for PSL or other good reasons would need to
follow the same rules, and thus may influence item 2.
4. For the integer-to-boolean conversion case, my preference is for 0 or
less to map to 'false', and 1 or above to map to 'true'. This has merit for
unsigned counters etc., but if others know better reasons for other mappings
then I would concede.
5. There may be issues arising from many engineers not having English (of
any variant) as a first language, and others who do being more numerate than
literate. That may be the reason for such beauties as:
if (boolean_signal = true) then
6. I suspect that no language can eliminate sloppy designing causing broken
designs, but a good language facilitates good designs, and it must be better
that VHDL includes all the features that are required, especially as you
don't have to use the features you don't need (such as real numbers and
textio in the synthesizable parts). Strong typing is IMHO good, but doesn't
get killed by constrained use of well-thought-out implicit type conversions.
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