RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing

Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing
From: Scott Thibault (thibault@gmvhdl.com)
Date: Fri Dec 19 2003 - 07:04:30 PST

>
> I think that in VHDL in general this does not save significant typing
> and does not add much value, however when you consider PSL assertions
>

I don't think typing is the real benefit here. I don't think I have ever
mistakenly typed:
        if (we = '0') then
or
        if (we_n = '1') then

However, I have many many times typed:
        if (we) then

The result being that when I finally compile the design, I'm met with a long
list of compiler errors. This is frustrating and reduces productivity.

--Scott Thibault
Green Mountain
Computing Systems, Inc.
http://www.gmvhdl.com

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