Subject: RE: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Bailey, Stephen (SBailey@model.com)
Date: Thu Dec 18 2003 - 23:13:18 PST
Hamish,
> > We actually discussed an alternative way to arrive at the same
> > functionality. Since people seem to be hung up on this
> implicit call
> > and cannot make the connection to how it is just a tiny extension to
> > operator overloading capabilities already in the language:
>
> I don't agree. The "cond" operator is certainly just an
> example of the
> overloading that VHDL already has - the implicit call is IMHO
> unrelated,
> and the part that most object to.
Both Jim and I have attempted to demonstrate how this is nearly identical to operator overload resolution. I'm sorry we have failed to convince you that it is. I can't think of any better examples.
> >> By the way, does the implicit "COND" call only apply to if? What
> >> about assignments to boolean, as in
> >>
> >> signal z: boolean; signal x, y: bit;
> >>
> >> begin z <= x and y; end if;
> >>
> >> Logically this should work too, if it works with if.
> >
> > No, it does not logically work because this is NOT a condition
> > context. There is no explicit context (nothing in the syntax that
> > indicates that the LHS is boolean) which makes it obvious that the
> > result of the RHS should be converted to boolean.
> >
> > We did not want the proposal to apply to this situation and it does
> > not.
>
> I think this would make the overall language *feel*
> inconsistent. In one
> place you have automatic conversion from other types to
> boolean, but not
> in an assignment. I guess you could write
>
> z <= true when (x and y) else false;
>
> although that fails your non-verbosity test.
This comment is out-of-line. We have demonstrated repeatedly that we are not reducing typing simply for the sake of reducing typing. Your example is obviously contrived as most people would simply write:
z <= to_boolean(x and y); -- choose the name of your conversion function
But, in the bigger view, I think we (the fast-track team) are in general agreement with most of the commentators on this proposal thread that applying implicit conversion in contexts outside of *condition* does detract from the strong-typing, readability/maintainability features of the language. (We have stated numerous times why we think it is acceptable within the condition context.)
Personally, I don't find it inconsistent. As a VHDL trainer, Jim can add his opinion based on loads of experience. My assessment is that it is easy to explain and understand that the implicit boolean conversion applies only within the contexts permitted because they are contexts which syntactically require a boolean value. The assignment context, general complex expressions, etc. do not have any syntactic keys that indicate what the type of the result must be.
-Steve Bailey
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