Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Thu Dec 18 2003 - 22:49:45 PST
Bailey, Stephen wrote:
> We actually discussed an alternative way to arrive at the same
> functionality. Since people seem to be hung up on this implicit call
> and cannot make the connection to how it is just a tiny extension to
> operator overloading capabilities already in the language:
I don't agree. The "cond" operator is certainly just an example of the
overloading that VHDL already has - the implicit call is IMHO unrelated,
and the part that most object to.
>> By the way, does the implicit "COND" call only apply to if? What
>> about assignments to boolean, as in
>>
>> signal z: boolean; signal x, y: bit;
>>
>> begin z <= x and y; end if;
>>
>> Logically this should work too, if it works with if.
>
> No, it does not logically work because this is NOT a condition
> context. There is no explicit context (nothing in the syntax that
> indicates that the LHS is boolean) which makes it obvious that the
> result of the RHS should be converted to boolean.
>
> We did not want the proposal to apply to this situation and it does
> not.
I think this would make the overall language *feel* inconsistent. In one
place you have automatic conversion from other types to boolean, but not
in an assignment. I guess you could write
z <= true when (x and y) else false;
although that fails your non-verbosity test.
Cheers
Hamish
-- Hamish Moffatt R&D Engineer Data Networks Division Agilent Technologies +61 3 9210 5782 (T210 5782) Tel
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