Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typin g
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Thu Dec 18 2003 - 23:34:53 PST
Bailey, Stephen wrote:
>>> We actually discussed an alternative way to arrive at the same
>>> functionality. Since people seem to be hung up on this
[..]
>>
>> I don't agree. The "cond" operator is certainly just an example of
>> the overloading that VHDL already has - the implicit call is IMHO
>> unrelated, and the part that most object to.
>
> Both Jim and I have attempted to demonstrate how this is nearly
> identical to operator overload resolution. I'm sorry we have failed
> to convince you that it is. I can't think of any better examples.
I read through and understood your alternative explanation. I did not
find it plausible when you start by proposing to define "if" as an
operator! In that case you would expect to be able to use it anywhere an
operator is used.
> Personally, I don't find it inconsistent. As a VHDL trainer, Jim can
> add his opinion based on loads of experience. My assessment is that
> it is easy to explain and understand that the implicit boolean
> conversion applies only within the contexts permitted because they
> are contexts which syntactically require a boolean value. The
> assignment context, general complex expressions, etc. do not have any
> syntactic keys that indicate what the type of the result must be.
Fine. I am not writing tools to use the language, nor training others
formally. I am only trying to offer the opinion of someone who is using
it for both simulation and synthesis to design digital circuits.
I think we need to see Jim's full proposal on the operators etc before
we can discuss this more in a productive fashion. We're clearly not
going to agree on whether or not this is a good idea at this point.
Hamish
This archive was generated by hypermail 2b28 : Thu Dec 18 2003 - 23:36:48 PST