Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing

Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing
From: Jim Lewis (
Date: Thu Dec 18 2003 - 17:39:46 PST

Your misunderstanding here is my fault. I ment to
put the proposed overloading in it too. Note, I will
be posting the complete updated proposal soon.

   Overload binary logic operators to support the following:
      L R return
      bit bool bit
      bool bit bit
      sul bool sul
      bool sul sul

      But not overload the following as they will be ambiguous
      bool bool bit
      bool bool sul

So the following does use the implicit "COND" operator:
>> if Cs1 and Cs2 then -- if2

For the big picture to work, allowing sul and sul to return
bool will result in ambiguous expressions. For example:

     signal A, B, C, D : bit ;

     if (A and B) and (C and D) then

   Suppose we had the following overloading,
      L R return
      bit bit bit -- Already have this
      bit bit bool -- what if we had this too.

In the above it could be:
                  (A and B) and (C and D)
result type bool bool
result type bit bit

Processed in this way, this is ambiguous.

Note, I have seen an expression similar to this
be ambiguous with the parentheses and not without
the parentheses.


P.S. this also means that the following does not work:
> signal z: boolean;
> signal x, y: bit;
> begin
> z <= x and y;
> end if;

Jim Lewis
Director of Training   
SynthWorks Design Inc. 

Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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