Subject: Re: [vhdl-200x] Implicit conversion, Overloading, & Strong Typing
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Thu Dec 18 2003 - 17:10:37 PST
Jim Lewis wrote:
> Actually, I believe you are comfortable with this
> behavior, you are just stuck on "implicit".
> Let me give an example:
>
> signal A, Y : unsigned (8 downto 0) ;
>
> Y <= A + "000001111" ;
> vs.
> Y <= A + 15 ;
>
> This is overloading. The compiler picks the right "+" operator
> to call based on the equation and we are happy. It only knows
> which one to call based on type of the operands.
>
>
> Likewise:
> if Cs = '1' and Cs2 = '1' then -- if1
> vs.
> if Cs1 and Cs2 then -- if2
>
> Here the compiler also picks the right "COND" operator for the
> expression. For the first one (if1), it sees the top
> expression is boolean so it realizes it does not need to call "COND".
In the first example, you specifically called "+" and expected the
compiler to find the right one. In the second example you called AND it
find the right one too. That's fine and quite logical.
But you didn't explicitly called "COND" at all. That's foreign to VHDL.
By the way, does the implicit "COND" call only apply to if? What about
assignments to boolean, as in
signal z: boolean;
signal x, y: bit;
begin
z <= x and y;
end if;
Logically this should work too, if it works with if.
Cheers
Hamish
-- Hamish Moffatt R&D Engineer Data Networks Division Agilent Technologies +61 3 9210 5782 (T210 5782) Tel
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