Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting,San Jose Dec 4,2003
From: Marcus Harnisch (marcus_harnisch@mint-tech.com)
Date: Thu Dec 11 2003 - 07:52:01 PST
Jim Lewis writes:
> BTW, the language does not prevent you from mixing numeric_std
> with std_logic_unsigned. Hopefully this will be cleaned up in a
> more user friendly way by either providing numeric_std_unsigned
> (or similar name) or make bit_vector and std_logic_vector be
> unsigned.
I know. But adding the references to a file by hand at least points
your nose right to the problem. With a stack of
company/department/project/design contexts, this is very error
prone. I am afraid this is a situation we have to deal with. Adding
contexts and using them appropriately adds *a lot* of value.
Best regards,
Marcus
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