Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4,2003

Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4,2003
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Dec 10 2003 - 10:46:18 PST

Marcus Harnisch wrote:
> > > - Context Clause Design Unit
> > >
> I have no objections to that feature. Quite the contrary actually. But
> this scheme will make it easier to unknowingly create conflicting
> situations. Visibility is probably an issue to think about when
> implementing new contexts. Think of a global context referencing
> numeric_std, and a local context adding std_logic_unsigned for
> instance. Strictly speaking, before implementing a context a user
> would have to examine all included contexts and track changes to them.
Yes.
It is a matter of methodology. Many companies have methodology
police who dictate what one is permitted to use.

BTW, the language does not prevent you from mixing numeric_std
with std_logic_unsigned. Hopefully this will be cleaned up in a
more user friendly way by either providing numeric_std_unsigned
(or similar name) or make bit_vector and std_logic_vector be
unsigned.

Mixing numeric_std and std_logic_arith would create interesting
error messages when trying to use the types signed and unsigned.
However, this is also permitted. Especially if one uses the
full reference to the type ieee.std_logic_arith.signed vs
ieee.numeric_std.signed.

>
> > > - Signal Spy
I think the language states it is ':'. If not, this needs
to be cleaned up.

Cheers,
Jim 

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Jim Lewis
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