Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003

Subject: Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Dec 10 2003 - 23:15:54 PST

Rick,
The following example was ment as illustrative
as a place where we have more than one way to
say basically the same thing. These were not
discussed in VHDL-200X as they are part of 1076.6.

>> past: wait until Clk = '1' and Clk'event ;
>> current1: wait until Clk = '1' ;
>> current2: wait until rising_edge(Clk) ;
>> future: wait until rising_edge(Clk) and load_enable = '1' ;

While there are some potential simulation differences
if clock is not well behaved, from a RTL synthesis
perspective, current1 and current2 are the same.

Cheers,
Jim 

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This archive was generated by hypermail 2b28 : Wed Dec 10 2003 - 23:17:25 PST